#ifndef _HCIT_PARTHUS_CHIMERA_SPI_H
#define _HCIT_PARTHUS_CHIMERA_SPI_H

/******************************************************************************
 * MODULE NAME:  Hvit_chimera_spi.h
 * PROJECT CODE: BlueStream
 * DESCRIPTION:  HCI SPI driver for Chimera
 * AUTHOR:       Lu Gongyu
 * DATE:         06 March 2008
 *
 * SOURCE CONTROL: $Id: hcit_rda5868_spi.h,v 1.5 2008/11/26 03:09:43 tianwq Exp $
 *
 * NOTE TO USERS: In this driver, the constants XR7_HCIT are used. These do not identify
 *                any particular UART on the XR7 (there are two). To use the other UART,
 *                the XR7_HCIT_UART should be changed appropriately in the sys_hal_features.h header file.
 *                Also, the baud rate and receive FIFO trigger level are found here.
 *
 ******************************************************************************/

#include "sys_config.h"
#include "sys_types.h"
#include "sys_features.h"
#include "sys_rda_arm.h"

#define XR7_HCIT_SPI_BASE    RDA_AHB_SPI_BASE /* SPI Base Address */
/*
 * Offsets of registers
 */

#define XR7_SPI_FIFO                    0x00
#define XR7_SPI_CTL                     0x04
#define XR7_SPI_STATUS                  0x08
#define XR7_SPI_RCV_INT_EN              0x0C
#define XR7_SPI_TRANS_INT_EN            0x10

#define XR7_SPI_CTL_SPI_ENABLE          0x01
#define XR7_SPI_CTL_SPI_DISABLE         0x00
#define XR7_SPI_CTL_LSB_ENABLE          0x02
#define XR7_SPI_CTL_MSB_ENABLE          0x00
#define XR7_SPI_CTL_MISO_ENABLE         0x04
#define XR7_SPI_CTL_FLUSH               0x08

#define XR7_SPI_STATUS_RX_FIFO_INT_FLAG 0x400

#define XR7_SPI_TRANS_TRIG_0               0
#define XR7_SPI_RECV_TRIG_0                0
#define XR7_SPI_RECV_TRIG_1                1
#define XR7_SPI_RECV_TRIG_2                2
#define XR7_SPI_RECV_TRIG_4                4
#define XR7_SPI_RECV_TRIG_8                8
#define XR7_SPI_RECV_TRIG_16              16
#define XR7_SPI_RECV_TRIG_32              32
#define XR7_SPI_RECV_TRIG_100            100
#define XR7_SPI_RECV_TRIG_254            254
#define XR7_SPI_RECV_TRIG_255            255
#define XR7_SPI_RECV_TRIG_400            400
#define XR7_SPI_RECV_TRIG_480            480


#define HCIT_CHIMERA_SPI_TX_FIFO_LENGTH 512
#define HCIT_CHIMERA_SPI_RX_FIFO_LENGTH 512

/*
 * Line status LSR
 */

#define XR7_LSR_TEMT                0x40
#define XR7_LSR_THRE                0x20
#define XR7_LSR_BI                  0x10
#define XR7_LSR_FE                  0x08
#define XR7_LSR_PE                  0x04
#define XR7_LSR_OE                  0x02
#define XR7_LSR_DR                  0x01

/*
 * SPI register access macro
 */

#define mHCIT_CHIMERA_SPI_GET_REG(x)      (*(volatile u_int32*)(XR7_HCIT_SPI_BASE + (x)))
#define mHCIT_CHIMERA_SPI_SET_REG(r,x)    (*(volatile u_int32*)(XR7_HCIT_SPI_BASE + (r))) = (u_int32)(x)


/*
 * Function Interfaces
 */

void HCIT_Chimera_SPI_Initialise(u_int32 speed, u_int32 setting);
void HCIT_Chimera_SPI_Shutdown(void);

void HCIT_Chimera_SPI_Tx_Block(volatile u_int8 **bufp, volatile u_int32 *length, u_int8 flag, void (*txcb)(void));
#if TRA_HCIT_UART_POLLED_TX_SUPPORTED == 1
void HCIT_Chimera_SPI_Tx_Char_Polled(volatile u_int8 **buf, volatile u_int32 *length, u_int8 flag);
#endif

void HCIT_Chimera_SPI_Setup(volatile u_int8 *rx_buffer, u_int16 rx_length, u_int8 flag);

u_int16 HCIT_Chimera_SPI_Get_Char(void);

void HCIT_Chimera_SPI_Interrupt_Handler(void);
void HCIT_Chimera_SPI_Empty_FIFO(void);

#endif
